Dynamic programmable logic arrays (PLA's) are useful in the digital computer arts and in the digital control system arts for solving various logical relationships and providing various manufacturing and process control functions at reduced power dissipation and increased throughput performance. A dynamic programmable logic array (PLA) is sometimes referred to as a "clocked" PLA. A dynamic PLA requires a set of consecutive clocking pulses to be applied to it in order to produce a valid output. It is necessary to do this to obtain a valid output each time the input signal conditions for the PLA are changed. This is sometimes referred to as "validation" of the PLA output. In a typical example, four consecutive clocking pulses are required to obtain a valid output.
If a dynamic PLA is allowed to remain idle (no clocking pulses for validation purposes), the capacitive output stages of the PLA will begin to discharge. If this idle condition continues for a relatively long period of time, on the order of several microseconds, the output stages of the PLA will have discharged sufficiently so that the output data is no longer reliable. If the period of time since the last validation of the PLA output starts to become excessive, loss of output data can be prevented by supplying a set of consecutive clocking pulses to the PLA for purposes of refreshing the PLA output. So long as the PLA remains idle, it must be refreshed at periodic intervals to prevent loss of data.
A straightforward approach to generating the reoccurring sets of clocking pulses for a dynamic PLA would be to employ a hardware counter and the appropriate sequential control circuitry for generating a set of clocking pulses when requested for validation purposes or when needed for refresh purposes. The counter could be employed to count the number of pulses allowed to issue from a clock pulse source or, alternatively, a clock pulse source could be used to drive the counter with appropriate decoding circuitry being coupled to the output of the counter for producing the desired set of clocking pulses. In either case, the circuitry for producing the reoccurring sets of clocking pulses must include means for starting and stopping the production of the clocking pulses and means for synchronizing the production of the clocking pulses with the operation of the remainder of the system.
A digital control unit of considerably improved performance can be provided by using multiple dynamic PLA's wherein the validation intervals for the PLA's are overlapped to produce valid PLA output signals at a faster rate than would be the case for a single PLA. In this case, multiple sets of consecutive clocking pulses are needed to validate the different ones of the multiple dynamic PLA's. In general, the clocking pulse generation conditions are unique and different for each of the multiple PLA's. This would require the use of several hardware counters, each with its associated start/stop and synchronization problems, these problems being characteristic of sequential type circuits.
While useful in some applications, this multiple counter approach has various drawbacks. For one thing, this multiple counter circuitry is relatively expensive to build because of its complexity and its sequential circuit problems. Also, it is not easily adaptable to logic design changes.